Numworks Epsilon  1.4.1
Graphing Calculator Operating System
isr.c
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1 #include "rt0.h"
2 extern const void * _stack_start;
3 
4 /* Interrupt Service Routines are void->void functions */
5 typedef void(*ISR)(void);
6 
7 /* Notice: The Cortex-M4 expects all jumps to be made at an odd address when
8  * jumping to Thumb code. For example, if you want to execute Thumb code at
9  * address 0x100, you'll have to jump to 0x101. Luckily, this idiosyncrasy is
10  * properly handled by the C compiler that will generate proper addresses when
11  * using function pointers. */
12 
13 #define INITIALISATION_VECTOR_SIZE 0x71
14 
15 ISR InitialisationVector[INITIALISATION_VECTOR_SIZE]
16  __attribute__((section(".isr_vector_table")))
17  = {
18  (ISR)&_stack_start, // Stack start
19  start, // Reset service routine,
20  0, // NMI service routine,
21  abort, // HardFault service routine,
22  0, // MemManage service routine,
23  0, // BusFault service routine,
24  0, // UsageFault service routine,
25  0, 0, 0, 0, // Reserved
26  0, // SVCall service routine,
27  0, // DebugMonitor service routine,
28  0, // Reserved
29  0, // PendSV service routine,
30  0, // SysTick service routine
31  0, // WWDG service routine
32  0, // PVD service routine
33  0, // TampStamp service routine
34  0, // RtcWakeup service routine
35  0, // Flash service routine
36  0, // RCC service routine
37  0, // EXTI0 service routine
38  0, // EXTI1 service routine
39  0, // EXTI2 service routine
40  0, // EXTI3 service routine
41  0, // EXTI4 service routine
42  0, // DMA1Stream0 service routine
43  0, // DMA1Stream1 service routine
44  0, // DMA1Stream2 service routine
45  0, // DMA1Stream3 service routine
46  0, // DMA1Stream4 service routine
47  0, // DMA1Stream5 service routine
48  0, // DMA1Stream6 service routine
49  0, // ADC1 global interrupt
50  0, // CAN1 TX interrupt
51  0, // CAN1 RX0 interrupt
52  0, // CAN1 RX1 interrupt
53  0, // CAN1 SCE interrupt
54  0, // EXTI Line[9:5] interrupts
55  0, // TIM1 Break interrupt and TIM9 global interrupt
56  0, // TIM1 update interrupt and TIM10 global interrupt
57  0, // TIM1 Trigger & Commutation interrupts and TIM11 global interrupt
58  0, // TIM1 Capture Compare interrupt
59  0, // TIM2 global interrupt
60  0, // TIM3 global interrupt
61  0, // TIM4 global interrupt
62  0, // I2C1 global event interrupt
63  0, // I2C1 global error interrupt
64  0, // I2C2 global event interrupt
65  0, // I2C2 global error interrupt
66  0, // SPI1 global interrupt
67  0, // SPI2 global interrupt
68  0, // USART1 global interrupt
69  0, // USART2 global interrupt
70  0, // USART3 global interrupt
71  0, // EXTI Line[15:10] interrupts
72  0, // EXTI Line 17 interrupt RTC Alarms (A and B) through EXTI line interrupt
73  0, // EXTI Line 18 interrupt / USB On-The-Go FS Wakeup through EXTI line interrupt
74  0, // TIM8 Break interrupt TIM12 global interrupt
75  0, // TIM8 Update interrupt TIM13 global interrupt
76  0, // TIM8 Trigger & Commutation interrupt TIM14 global interrupt
77  0, // TIM8 Cap/Com interrupt
78  0, // DMA1 global interrupt Channel 7
79  0, // FSMC global interrupt
80  0, // SDIO global interrupt
81  0, // TIM5 global interrupt
82  0, // SPI3 global interrupt
83  0, // ?
84  0, // ?
85  0, // TIM6 global interrupt
86  0, // TIM7 global interrupt
87  0, // DMA2 Stream0 global interrupt
88  0, // DMA2 Stream1 global interrupt
89  0, // DMA2 Stream2 global interrupt
90  0, // DMA2 Stream3 global interrupt
91  0, // DMA2 Stream4 global interrupt
92  0, // SD filter0 global interrupt
93  0, // SD filter1 global interrupt
94  0, // CAN2 TX interrupt
95  0, // BXCAN2 RX0 interrupt
96  0, // BXCAN2 RX1 interrupt
97  0, // CAN2 SCE interrupt
98  0, // USB On The Go FS global interrupt
99  0, // DMA2 Stream5 global interrupts
100  0, // DMA2 Stream6 global interrupt
101  0, // DMA2 Stream7 global interrupt
102  0, // USART6 global interrupt
103  0, // I2C3 event interrupt
104  0, // I2C3 error interrupt
105  0, // ?
106  0, // ?
107  0, // ?
108  0, // ?
109  0, // ?
110  0, // ?
111  0, // RNG global interrupt
112  0, // FPU global interrupt
113  0, // ?
114  0, // ?
115  0, // SPI4 global interrupt
116  0, // SPI5 global interrupt
117  0, // ?
118  0, // ?
119  0, // ?
120  0, // ?
121  0, // ?
122  0, // ?
123  0, // Quad-SPI global interrupt
124  0, // ?
125  0, // ?
126  0, // I2CFMP1 event interrupt
127  0 // I2CFMP1 error interrupt
128 };
_stack_start
const void * _stack_start
ISR
void(* ISR)(void)
Definition: isr.c:5
start
void start()
Definition: rt0.cpp:31
INITIALISATION_VECTOR_SIZE
#define INITIALISATION_VECTOR_SIZE
Definition: isr.c:13
abort
void abort()
Definition: rt0.cpp:22
__attribute__
ISR InitialisationVector [INITIALISATION_VECTOR_SIZE] __attribute__((section(".isr_vector_table")))